How to make sure a clocked operation happens just once in Vhdl

title may be a bit confusing but what I try to do is to take data from ram/modify it and put that data back to the ram. I want all of this to happen just for the operation(Brightness/Contrast) time when I enable the system instead of happening over and over to the point where data becomes deformed. Here is the code. I want write_enable(which enables writing to ram) to stay at 1 just for the operation(in a window which I call cursor) time then go back to 0 even if enable is 1. This is some image processing and I change brightness and contrast of the image in a window I call cursor. This change must happen for all pixels inside cursor just once. I tried many things(complex control mechanism) but failed due to vivado’s unused element removal issue.I am totally out of idea on how to do that. How can I construct such a control mechanism??? I put commends(from here/to here) to show where this problem takes place.

rst is input
clk and clk2 are different clock signals
done is signal
data_in_ram is ram input
output_of_operation is output of change of Brightness or contrast operation
data_rom is output of rom
PICTURE_WIDTH_HEIGHT is length of my square picture (250*250)
pos_x and pos_y are signals that denote pixel coordinates
cursor_pos_x and cursor_pos_y are upper-left coordinate of the window or cursor
length is length of the square window or cursor
clk is 25Mhz
clk2 is 50Mhz. this is chosen 50 due to ram's read latency(2 clock cycle)

The ram and rom below are constructed using block memory generator.

Reading_Writing_Resetting_Ram: process(clk2,clk,rst) is
begin

    if rst = '1' then    
      done <= '0';
    elsif rising_edge(clk) then    
        if done = '0' then
            if address_rom < conv_std_logic_vector((PICTURE_WIDTH_HEIGHT*PICTURE_WIDTH_HEIGHT),16) then
                write_enable <= '1';
                data_in_ram <= data_rom;
                address_ram <= address_rom;
                address_rom <= address_rom + 1;
            else
                address_rom <= (others => '0');
                write_enable <= '0';
                done <= '1';
            end if;
            -------------------------------------part above is for resetting ram
        else --if done = '1' --From here    
            if ( pos_x >= cursor_pos_x ) and (pos_x < cursor_pos_x + length) and ( pos_y >= cursor_pos_y) and (pos_y < cursor_pos_y + length) then --if within cursor

                address_ram <=(conv_std_logic_vector((pos_x + pos_y*PICTURE_WIDTH_HEIGHT),16));
                data_in_ram <= output_of_operation;   

                if enable = '1' then    
                    write_enable <= '1';
                else    
                    write_enable <= '0';    
                end if; -- enable    
            else --if out of cursor -- to here
                -------------------------- part below is for reading from ram
                write_enable <= '0';

                if (pos_x < PICTURE_WIDTH_HEIGHT) and (pos_y <PICTURE_WIDTH_HEIGHT) and (pos_x >= 0) and (pos_y >= 0) then -- if within picture

                    address_ram <=(conv_std_logic_vector((pos_x + pos_y*PICTURE_WIDTH_HEIGHT),16));

                end if; 
            end if; 
        end if; 
    end if;    
end process;

This code below is used for second condition for write_enable but vivado removes this components.

Adjusting_enable2: process(rst,clk,cursor_pos_x,cursor_pos_y,enable,cursor_mode,current_cursor_mode,c_cursor_pos_x,c_cursor_pos_y) is
begin
if (rst = '1') or (cursor_mode /= current_cursor_mode) or (c_cursor_pos_x /= cursor_pos_x) or (c_cursor_pos_y /= cursor_pos_y)  then

enable2 <= '1';
c_cursor_pos_x <= cursor_pos_x;
c_cursor_pos_y <= cursor_pos_y;
counter_for_enable2 <= 0;

elsif rising_edge(clk) then

if enable ='1' then

if counter_for_enable2 < PICTURE_WIDTH_HEIGHT*PICTURE_WIDTH_HEIGHT then

counter_for_enable2 <= counter_for_enable2 + 1;

else

enable2 <= '0';

end if;
end if;
end if;
end process;