Modelsim signal declaration issue

Question

With Modelsim I would like to test a code but one signal always remains uninitialized. Here a code snipped to explain the problem with Modelsim:

-- Signal Declaration
signal shifter          : std_logic_vector(0 to 6);
signal led_out_temp         : std_logic;

process (reset_reset_n) is
begin
    if reset_reset_n = '0' then
        shifter <= (others => '0');  -- After reset_reset_n goes to '0' shifter is '0000000'
        led_out_temp <= '0';         -- Always has the value 'U'
    end if;
end process;

When I step through it I can check the values but even after stepping out of the process the signal "led_out_temp" is 'U'. Can someone tell me why?

Thanks!

vineeshvs · Answer

Two possible methods to check the design

Write a testbench where you assign reset_reset_n to zero
Simulate the design in Modelsim without a testbench and force the value of reset_reset_n to zero before running the simulation

Is shifter becoming zero in your try? If it's also not going to zero, then you might not have gone inside the if loop.

[Edit: Including sample testbench format]

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY test_tb IS
END test_tb;

ARCHITECTURE behavior OF test_tb IS

   -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT name_of_your_design
    PORT(
         reset_reset_n : IN  std_logic;
         input2 : IN  std_logic
         output : OUT  std_logic_vector(3 downto 0);
        );
    END COMPONENT;

   -- Signal initializations
   signal reset_reset_n_sig : std_logic := '0';
   signal input2_sig : std_logic := '0';
   signal output_sig : std_logic_vector(3 downto 0);

BEGIN

    -- Port mapping
   instance_name: name_of_your_design PORT MAP (
         reset_reset_n => reset_reset_n_sig
         input2  => input2_sig,
         ouput => output_sig
        );

  -- Give your test inputs here
  process_to_give_test_inputs: process
   begin        
        wait for 7 ns;
        reset_reset_n <='1';
        wait for 3 ns;
        reset_reset_n <='0';
        wait;
  end process;

END;

Ref: https://vhdlguru.blogspot.com/2011/06/vhdl-code-for-4-tap-fir-filter.html

Thanks: @morteza kavakebi

Modelsim signal declaration issue

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