PCIExpress configuration header space. What are I/O space enable and memory space enable layouts in command register means

I am new to PCIe.

In the latest specifications of PCI/PCIe 5.0 the description for I/O space enable and memory space enable layouts in command register field is the following:

I/O Space Enable – Controls a Function’s response to I/O Space accesses. When this bit is Clear, all
received I/O accesses are caused to be handled as Unsupported Requests. When this bit is Set, the
Function is enabled to decode the address and further process I/O Space accesses. For a Function with a
Type 1 Configuration Space Header, this bit controls the response to I/O Space accesses received on its
Primary Side.
Default value of this bit is 0b.
This bit is permitted to be hardwired to 0b if a Function does not support I/O Space accesses.

Memory Space Enable – Controls a Function’s response to Memory Space accesses. When this bit is
Clear, all received Memory Space accesses are caused to be handled as Unsupported Requests. When
this bit is Set, the Function is enabled to decode the address and further process Memory Space accesses. For a Function with a Type 1 Configuration Space Header, this bit controls the response to
Memory Space accesses received on its Primary Side.
Default value of this bit is 0b.
This bit is permitted to be hardwired to 0b if a Function does not support Memory Space accesses.

My understanding is that the processor is capable of accessing the config space of each function through the MMCFG mechanism.

Actually what is "response to I/O space access" means? since the CPU is supposed to access that 4k space through the base address that is mapped in the system’s address space.

Thank you